1. Field of the Invention
The present invention relates to a variable gain amplifier, and in particular, to a so-called Linear-in-dB variable gain amplifier (VGA) that approximates a change in a decibel value of a gain with respect to a linear change of a control signal to an approximate linear relationship by using a switched capacitor system for changing a ratio of capacitive loads by changing a switch in accordance with a control signal.
2. Description of the Related Art
Hereinafter, a conventional variable gain amplifier (VGA) will be described with reference to FIGS. 5A, 5B, 6, 7, and 8. Such a VGA is described in “CMOS analog front-end chip set for a multiple pixel CCD video camera” by Kenichi Nishio, Tetsuya Senda, et al. (TECHNICAL REPORT OF IEICE. ICD2000-84(2000-09)).
FIGS. 5A and 5B respectively are a circuit diagram showing an exemplary configuration of a conventional VGA and a timing chart of clock signals Φ1 and Φ2 applied to the circuit shown in FIG. 5A.
In FIG. 5A, reference numeral 1 denotes external input terminals for differential signals Vin+, Vin−, 2 denotes external output terminals for differential signals Vout+, Vout−, 3 denotes DC bias application terminals, 4 denotes a differential amplifier of a differential input/output type, 24 denotes input side capacitor strings, 25 denotes output side capacitor strings, 7, 8, 11, 13 denote switches that are turned on/off at a timing of the first clock signal Φ1 shown in FIG. 5B, and 9, 10 denote switches that are turned on/off at a timing of the second clock signal Φ2 shown in FIG. 5B.
The differential signals Vin+, Vin− input from the external input terminals 1 are accumulated in the input side capacitor strings 24 as charge via the switches 7 that are turned on at a timing (e.g., logic “High” level) of the first clock signal Φ1. Simultaneously, the switches 11 are turned on, and DC biases Vdc input from the DC bias application terminals 3 are accumulated in the output side capacitor strings 25 as charge. At this time, the switches 13 also are turned on, whereby the external output terminals 2 are short-circuited with respect to the DC bias application terminals 3.
Next, when the second clock signal Φ2 becomes a “High” level (the first clock signal is at a logic “Low” level), the switches 9, 10 are turned on, and the signal input terminal sides of the input side capacitor strings 24 are short-circuited by the switches 9, whereby differential charges of two input side capacitor strings are transferred to the output side capacitor strings 25. At this time, differential signals Vout+ and Vout− amplified by a ratio of capacitance Cin of the input side capacitor strings 24 and capacitance Cout of the output side capacitor strings 25 (i.e., Cin/Cout) are output from the external output terminals 2.
FIG. 6 is an equivalent circuit diagram of the input side capacitor string 24 and the output side capacitor string 25 in the VGA shown in FIG. 5A. In FIG. 6, the same components as those in FIG. 6A are denoted with the same reference numerals and symbols as those therein, and the description thereof will be omitted.
In FIG. 6, reference numeral 5 denotes an input fixed capacitor (Cs), 6 denotes a feedback loop fixed capacitor (Cf), 14 denotes a higher order capacitor string composed of n capacitors, 15 denotes a lower order capacitor string composed of m capacitors, 16 denotes a higher order control switch string composed of n switches, 17 denotes a lower order control switch string composed of m switches, 18 denotes a coupling capacitor (Cc) connected between a common connection terminal tp of the higher order capacitor string 14 and a common connection terminal tp of the lower order capacitor string 15, and 19 denotes a control bus line terminal that controls switching of the higher order control switch string 16 and the lower order control switch string 17. The components denoted with the reference numerals 1 to 3 and 5 to 19 are placed similarly in the opposite side input/output of the differential amplifier 4. For convenience, the description thereof will be omitted.
The VGA shown in FIG. 6 has its gain controlled by a control signal of (n+m) bits composed of higher order n bits and lower order m bits from the control bus line terminal 19. Furthermore, the higher order capacitor string 14 is composed of n capacitors including Ct0, Ct1, Ct2, Ct3, . . . , Ct(n−1). Ct1, Ct2, Ct3, . . . , Ct(n−1) respectively have capacitances that are 2(=21), 4(=22), 8(=23), . . . , 2n−1 times the capacitance of Ct0. Similarly, the lower order capacitor string 15 is composed of m capacitors including Cb0, Cb1, Cb2, Cb3, . . . , Cb(m−1). Cb1, Cb2, Cb3, . . . , Cb(m−1) respectively have capacitances that are 2(=21), 4(=22), 8(=23), . . . , 2m−1 times the capacitance of Cb0. Furthermore, Ct0 of the higher order capacitor string 14, Cb0 of the lower order capacitor string 15, and the coupling capacitor 18 (Cc) have equal capacitances.
The higher order control switch string 16 is composed of n switches SWt0 to SWt (n−1), and switched with a control signal from the control bus line terminal 19. Similarly, the lower order control switch string 17 is composed of m switches SWb0 to SWb(m−1), and switched with a control signal from the control bus line terminal 19.
Each switch of the higher order control switch string 16 and the lower order control switch string 17 is connected to an a-side terminal or a b-side terminal with a control signal from the control bus line terminal 19. The a-side terminal is connected to a point A on the external output terminal 2 side, and the b-side terminal is connected to a point B on the external input terminal 1 side. The control bus line terminal 19 has (m+n) control signal terminals DA0 to DA(m+n−1) so as to change each switch of the higher order control switch string 16 and the lower order control switch string 17.
When all the control signal terminals DA0 to DA(m+n−1) are at a logic “Low” level, all the switches of the higher order control switch string 16 and the lower order control switch string 17 are connected to the a-side terminal. When all the control signal terminals DA0 to DA(m+n−1) are at a logic “High” level, all the switches of the higher order control switch string 16 and the lower order control switch string 17 are connected to the b-side terminal. At this time, the higher order capacitor string 14 connected to the higher order control switch string 16 is connected in parallel to the input fixed capacitor 5 or the feedback loop fixed capacitor 6, and the lower order capacitor string 15 connected to the lower order control switch string 17 is connected in parallel to the input fixed capacitor 5 or the feedback loop fixed capacitor 6 via the coupling capacitor 18.
It is assumed that the setting of the (m+n) control signal terminals DA0 to DA(m+n−1) is Code. For example, when all the control signal terminals DA0 to DA(m+n−1) are at a logic “Low” level, Code=0. When only DA0 is at a logic “High” level, and DA1 to DA(m+n−1) are at a logic “Low” level, Code=1. When only DA1 is at a logic “High” level, and DA0, DA2 to DA(m+n−1) are at a logic “Low” level, Code=2. When DA0 and DA1 are at a logic “High” level, and DA2 to DA(m+n−1) are at a logic “Low” level, Code=3. Thus, when all the control signal terminals DA0 to DA(m+n−1) are at a logic “High” level, Code=2(m+n−1), whereby the connection of each switch of the higher order control switch string 16 and the lower order control switch string 17 can be switched with (m+n) bit levels.
Since the capacitance of the capacitor Ct0 of the higher order capacitor string 14, the capacitance of the capacitor Cb0 of the lower order capacitor string 15, and the capacitance of the coupling capacitor 18 (Cc) are equal to each other, it is assumed that these capacitances are represented by C. For example, when all the capacitors of the higher order capacitor string 14 and the lower order capacitor string 15 are connected to the point A (i.e., Code=0), a gain G of the VGA shown in FIG. 6 is represented by the following Formula (1):G=(2m·Cs+Code·C)/(2m·Cf+(2m+n−1−Code)·C)  (1)
FIG. 7 illustrates, as a specific example of the VGA in FIG. 6, the case where the gain G is controlled by the control signal terminals DA0 to DA8 of (m+n)=9 bits composed of higher order (n) 5 bits and lower order (m) 4 bits. In FIG. 7, the same components as those in FIG. 6 are denoted with the same reference numerals as those therein, and the description thereof will be omitted.
The gain G of the VGA shown in FIG. 7 is represented by the following Formula (2) from the above Formula (1):G=(16·Cs+Code·C)/(16·Cf+(511−Code)·C  (2)The gain is changed in a range of Code=0 to 511.
Recently, there is a demand for facilitating the design of a circuit or software used for controlling a VGA. This makes it necessary to provide a circuit in which the gain control characteristics of a VGA are represented by a simple operational formula, and there is a demand for gain control characteristics having a Linear-in-dB relationship approximately.
In the above-mentioned conventional VGA, the Code that is a control signal and the gain G are represented by simple operational formulas as in Formulas (1) and (2). However, in the case of designing a circuit having a gain variable range of 0 to 18 dB in the circuit shown in FIG. 7, the gain control characteristics are represented by a solid line in FIG. 8, which do not have an ideal Linear-in-dB relationship that changes at G=10(a·Code+b)/20 shown in FIG. 9.
Accordingly, there is a demand for gain control characteristics having an approximate Linear-in-dB relationship so as to facilitate the design of a circuit or software for controlling a VGA and to enhance the levels in which a gain can be controlled with a predetermined change amount in a wide range of control.